Today, workstations and computers are demanding faster memory subsystems in an effort to enhance system performance. This requires a fast memory access and fast sense amplifiers. In order to reduce power dissipation and allow greater memory chip densities, recent memory designs have utilized a reduced supply voltage. This has presented a special challenge to sense amplifier designers. One of the outcomes is a greater utilization of current-sense amplifiers versus the more conventional voltage-sense amplifiers. These amplifiers produce a larger voltage gain than voltage-sense amplifiers with the same supply voltage but the concomitant recovery time is also longer.
One article and two US patents are known which deal with the subject of sense amplifiers.
Katsuro Sasaki et al, "A 7 ns, 140 mw, CMOS (Complementary Metal Oxide Semiconductor) SRAM (Static Random Access Memory) with Current Sense Amplifier", IEEE Journal of Solid-state Circuits, vol. 27, No. 11, Nov. 1992, pp. 1511-1517 describes two types of current sense-amplifiers and a voltage-sense amplifier presented for comparison purposes. It proposes a PMOS (P-type MOS) bias type and an NMOS (N-type MOS) bias type current-sense amplifiers both of which offer high gain and operate near the saturation level.
U.S. Pat. No. 5,412,607 (Kusaba) discloses a two stage current-sense amplifier wherein the first stage current-sense amplifier has a high gain and requires no external bias which allows operation with reduced current consumption and thus high integration can be achieved.
U.S. Pat. No. 5,654,928 (Lee et al) discloses a high gain, low power current-sense amplifier wherein the amplifier is composed of two identical legs each leg consisting of a PMOS and an NMOS transistor connected in series. The gates of the PMOS transistors are cross coupled to the drains of the PMOS transistors and the gate of each NMOS transistor is cross coupled to the source of the PMOS transistor in the other leg.